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2010-2012 Microchip Technology Inc.

DS39977F-page 125

PIC18F66K80 FAMILY

6.4.3.2

FSR Registers and POSTINC,

POSTDEC, PREINC and PLUSW

In addition to the INDF operand, each FSR register pair

also has four additional indirect operands. Like INDF,

these are “virtual” registers that cannot be indirectly

read or written to. Accessing these registers actually

accesses the associated FSR register pair, but also

performs a specific action on its stored value.

These operands are:

POSTDEC – Accesses the FSR value, then

automatically decrements it by ‘1’ afterwards

POSTINC – Accesses the FSR value, then

automatically increments it by ‘1’ afterwards

PREINC – Increments the FSR value by ‘1’, then

uses it in the operation

PLUSW – Adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses

the new value in the operation

In this context, accessing an INDF register uses the

value in the FSR registers without changing them.

Similarly, accessing a PLUSW register gives the FSR

value, offset by the value in the W register, with neither

value actually changed in the operation. Accessing the

other virtual registers changes the value of the FSR

registers.

Operations on the FSRs with POSTDEC, POSTINC

and PREINC affect the entire register pair. Rollovers of

the FSRnL register, from FFh to 00h, carry over to the

FSRnH register. On the other hand, results of these

operations do not change the value of any flags in the

STATUS register (for example, Z, N and OV bits).

The PLUSW register can be used to implement a form

of Indexed Addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

6.4.3.3

Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs

or virtual registers represent special cases. For

example, using an FSR to point to one of the virtual

registers will not result in successful operations.

As a specific case, assume that the FSR0H:FSR0L

registers contain FE7h, the address of INDF1.

Attempts to read the value of the INDF1, using INDF0

as an operand, will return 00h. Attempts to write to

INDF1, using INDF0 as the operand, will result in a

NOP

On the other hand, using the virtual registers to write to

an FSR pair may not occur as planned. In these cases,

the value will be written to the FSR pair, but without any

incrementing or decrementing. Thus, writing to INDF2

or POSTDEC2 will write the same value to the

FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, however, particularly if their

code uses Indirect Addressing.

Similarly, operations by Indirect Addressing are gener-

ally permitted on all other SFRs. Users should exercise

the appropriate caution, so that they do not inadvertently

change settings that might affect the operation of the

device.

6.5

Program Memory and the

Extended Instruction Set

The operation of program memory is unaffected by the

use of the extended instruction set.

Enabling the extended instruction set adds five

additional two-word commands to the existing PIC18

instruction set: ADDFSR, CALLW, MOVSF, MOVSS and

SUBFSR

. These instructions are executed as described

in Section 6.2.4 “Two-Word Instructions”.

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